1. Technical Field
The present invention relate to an electrically erasable programmable read-only memory (EEPROM) cell, and more particularly, to an EEPROM cell and methods for forming and reading the EEPROM cell.
2. Discussion of the Related Art
An electrically erasable programmable read-only memory (EEPROM) device is a memory device that may be electrically programmed and erased. EEPROMs may be able to maintain stored data even in the absence of supplied power.
An EEPROM device in which one transistor constitutes a single memory cell may be referred to as a 1T type flash memory device. An EEPROM device in which two transistors constitute a single memory cell may be referred to as a 2T type flash memory device. For 2T type flash memory devices, the two transistors of the memory cell may include a selection transistor and a memory transistor. Other forms of EEPROM may include a split gate type memory device, a floating gate tunnel oxide (FLOTOX) type memory device, etc.
The 1T type flash memory device may have a small size owing to the fact that each single memory cell includes just one transistor. Accordingly, the 1T type flash memory device may be highly integrated. However, the 1T type flash memory device may be less reliable than the 2T type flash memory device. Thus, the 2T type flash memory device is widely used in a logic device requiring high reliability.
Modern applications require EEPROM devices having large memory capacities and small sizes. Shrinking the size of EEPROM devices has lead to a narrow active region. For example, the gate length of the memory cell transistor has now become narrow. As a result, the capacitance of the memory cell has lowered. The low capacitance of the memory cell may cause low programming and erasing efficiency, such that a threshold voltage of the memory cell under an “On” state may be increased, thereby reducing an on-cell current.
Particularly, the increased write cycle may include repeatedly programming and erasing data in the memory cell so that the threshold voltage of the memory cell may be increased to decrease the on-cell current. When the on-cell current is decreased, a sense amplifier, which may determine the data in the memory cell in accordance with the on-cell current, may fail to discriminate the “On” state, and thus operational failures may be generated.
To overcome the above-mentioned problem, methods of improving characteristics of a tunnel oxide layer in the memory cell through which charges pass have been developed. Accordingly, although programming and erasing the data in the memory cell are repeatedly performed, the threshold voltage of the memory cell may be prevented from increasing by improving the characteristics of the tunnel oxide layer. The tunnel oxide layer having the improved characteristics may prevent the on-cell current from being lowered below an initial on-cell current. However, the tunnel oxide layer having the improved characteristics may not increase the initial on-cell current.
Further, in the memory cell of the 2T type memory device, when data in the memory cell is read, the selection transistor may be provided with efficient capacity in order to increase the on-cell current. The on-cell current may be determined in accordance with the characteristics of the selection transistor under a condition that the threshold voltage of the memory transistor in the memory cell is maintained at a low level in the “On” state.
However, the selection transistors may have a low operational voltage as well as a short gate length and a short gate width. Thus, a current passing through the selection transistor may be relatively small. Therefore, increasing the on-cell current to aid the sense amplifier to discriminate the data may not sufficiently prevent reading failures.